VIA VT82C570M overview
VIA VT82C570M PCI Bus Controller Chipset The VT82C570M Apollo Master is a high performance, cost-effective and energy efficient chip set for the implementation ...
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Manufactured byVIA
Product groupPCI Bus Controller Chipsets
DescriptionVIA VT82C570M PCI Bus Controller Chipset
OverviewThe VT82C570M Apollo Master is a high performance, cost-effective and energy efficient chip set for the implementation of PCI/ISA desktop and notebook personal computer systems based on the 64-bit P54C/Pentium/K5/M1 super-scalar processors. Either 3.3v or 5v CPU and cache interface is supported up to 66Mhz CPU external bus speed (with CPU internal speed up to 150Mhz and above). In either case, DRAM, PCI and ISA bus runs at 5v voltage level.The VT82C570M chip set consists of the VT82C575M system controller, the VT82C576M PCI bus controller with integrated master mode Enhanced-IDE controller, and two instances of the VT82C577M data buffers. The CPU bus is minimally loaded with only the CPU, secondary cache and the chip set. The VT82C577M data buffers isolate the CPU bus from the DRAM, PCI and ISA bus so that CPU and cache operation may run reliably at the high frequencies demanded by today's processors. The chip set also interfaces directly with the VT82C416 integrated clock generator, real time clock with extended CMOS (128 byte) and keyboard controller with PS2 mouse support. A complete main board can be implemented with only ten TTLs. Please refer to Figure 1 for the system block diagram.The VT82C570M supports eight banks of DRAMs up to 512MB. The DRAM controller supports Standard Page Mode DRAM, EDO-DRAM and Burst EDO-DRAM in a flexible mixed/match manner. The eight banks of DRAM are grouped into four pairs with an arbitrary mixture of 256K/512K/1M/2M/4M/8M/16MxN DRAMs. Zero, one or both banks may be populated in each pair with either 32bit or 64bit data width.The secondary (L2) cache is based on Burst Synchronous (Pipelined or non-pipelined) SRAM, asynchronous SRAM or cache module from 128KB to 2MB. For burst synchronous SRAMs, 3-1-1-1 timing can be achieved for both read and write transactions at 66Mhz. For standard SRAMs, 3-2-2-2 and 4-2-2-2 timing can be achieved for interleaved read and write transactions at 66Mhz. Four levels of CPU/cache to DRAM write buffers with concurrent write-back capability are included in the VT82C577M data buffer chips to speed up the cache read and write miss cycles. For primary cache fill cycles that result in secondary cache misses, the primary and secondary caches are filled up concurrently to further enhance the performance.
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