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Product overview Micro Memory

MM-6230

Curtiss-Wright MM-6230 High Speed DRAM Memory VME Modul...

Curtiss-Wright MM-6230 High Speed DRAM Memory VME Modul...

Micro Memory MM-6230 overview

Micro Memory MM-6230 Memory Expansion ModuleFeatures Capacity: 4M, 8M, 12M, 16MB Cycle Time: 240 nsec Read/Write Access: 175 nsec/50 nsec (Fast Write) VMEbus-compatible with A32/A24, D32/D16/D8 (UAT) Block mode transfers for sequential access (BLT) Parity generation and checking for error detection ...

Manufactured byMicro Memory
Part number or familyMM-6230
Product groupModules

What is Micro Memory MM-6230?

Curtiss-Wright MM-6230 High Speed DRAM Memory VME Modul.... Micro Memory MM-6230 Memory Expansion ModuleFeatures Capacity: 4M, 8M, 12M, 16MB Cycle Time: 240 nsec Read/Write Access: 175 nsec/50 nsec (Fast Write) VMEbus-compatible with A32/A24, D32/D16/D8 (UAT) Block mode transfers for sequential access (BLT) Parity generation and checking for error detection ...

Product details

Manufactured byMicro Memory
Product groupModules
DescriptionMicro Memory MM-6230 Memory Expansion ModuleFeatures Capacity: 4M, 8M, 12M, 16MB Cycle Time: 240 nsec Read/Write Access: 175 nsec/50 nsec (Fast Write) VMEbus-compatible with A32/A24, D32/D16/D8 (UAT) Block mode transfers for sequential access (BLT) Parity generation and checking for error detection on each byte Module Selection on 64KB boundaries, switch-selectable upper and lower limits in each of the 16MB banks Six-bit address modifiers support user and supervisory modesThe MM-6230D main board is a high density memory module that provides 4M, 8M, 12M, or 16MB. The memory module is completely compatible with the VMEbus and supports A32/A24, D32/D16/D8, byte, word, long word, unaligned bus transfer (UAT) and Fast-Write cycles. It also supports sequential access block mode transfers (BLT) of 256 bytes.Module selection is on 64KB boundaries, whose upper and lower limits are switch-selectable. To simplify reprogramming, address modifiers are programmed and decoded in a socketed IFL.Parity generation and checking are provided for each byte. Parity status is stored and transmitted via BERR* signal. If the BERR* signal is asserted, the DTACK* signal is inhibited during memory read operations.Reliability is ensured by burn-in and running memory diagnostics that check operation for 48 hours while temperature-cycling boards from 0 to 60°C.

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