Intel 430HX overview
Intel 430HX (Triton II) System Controller Chipset Today’s technology does not meet tomorrow’s needs. With new applications such as multimedia, video conferencing, and on-line services; market requirements for the volume desktop computer will be higher performance, increased ease of use, and more...
What is Intel 430HX?
Intel 430HX (Triton II) System Controller Chipset. Intel 430HX (Triton II) System Controller Chipset Today’s technology does not meet tomorrow’s needs. With new applications such as multimedia, video conferencing, and on-line services; market requirements for the volume desktop computer will be higher performance, increased ease of use, and more...
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Manufactured byIntel
Product groupChipset
DescriptionIntel 430HX (Triton II) System Controller Chipset
IntroductionToday’s technology does not meet tomorrow’s needs. With new applications such as multimedia, video conferencing, and on-line services; market requirements for the volume desktop computer will be higher performance, increased ease of use, and more features—all at a lower system price. The Intel 430HX PCIset (430HX) redefines the mainstream PC by providing new performance, features, and support for emerging technologies. 430HX architecture maximizes PCI performance which allows for new performance levels, optimized multimedia support, and Plug and Play (PnP) support. A design based on a Pentium® processor Flexible Motherboard reduces time to market and minimizes cost to support upgradability and flexibility.The information provided in this design guide is based on a reference platform developed around the 430HX and the latest members of the Pentium processor family. Section 6.0 shows the schematics, jumper settings, component placement, and bill of materials.
OverviewThe Intel 430HX PCIset consists of the 82439HX System Controller (TXC) and the 82371SB PCI I/O IDE Xcelerator (PIIX3). The TXC is a single-chip host-to-PCI bridge and provides the second level cache control and DRAM control functions. The second level (L2) cache controller supports a write-back cache policy for cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The cache memory is implemented with synchronous pipelined burst SRAMs. An external Tag RAM is used for the address tag and an internal Tag RAM for the cache line status bits. The TXC provides a 64/72-bit data path to main memory and memory sizes up to 512 Mbytes. The DRAM controller provides eight rows and optional DRAM Error detection/correction or parity. The TXC’s optimized PCI interface allows the CPU to sustain the highest possible bandwidth to the graphics frame buffer at all frequencies. Using the snoop ahead feature, The TXC allows PCI masters to achieve full PCI bandwidth. For increased system performance, the TXC contains read prefetch and posted write buffers.
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