DYNAMIC ENGINEERING PMC-PARALLEL-485NRC1 overview
Dynamic Engineering PMC-PARALLEL-485NRC1 Digital Parallel Interface PMC Module with interrupt on change of state capability, upper bits muxed to allow input buffering or discrete outputs, and upper nibble predefined as output. PMC-PARALLEL-485 is part of the PCI Mezzanine Card [PMC] family of modula...
Manufactured byDYNAMIC ENGINEERING
Part number or familyPMC-PARALLEL-485NRC1
Product groupDigital Parallel Interface PMC Modules
What is DYNAMIC ENGINEERING PMC-PARALLEL-485NRC1?
Dynamic Engineering PMC-PARALLEL-485NRC1 Digital P.... Dynamic Engineering PMC-PARALLEL-485NRC1 Digital Parallel Interface PMC Module with interrupt on change of state capability, upper bits muxed to allow input buffering or discrete outputs, and upper nibble predefined as output. PMC-PARALLEL-485 is part of the PCI Mezzanine Card [PMC] family of modula...
Product details
Manufactured byDYNAMIC ENGINEERING
Product groupDigital Parallel Interface PMC Modules
DescriptionDynamic Engineering PMC-PARALLEL-485NRC1 Digital Parallel Interface PMC Module with interrupt on change of state capability, upper bits muxed to allow input buffering or discrete outputs, and upper nibble predefined as output.
OverviewPMC-PARALLEL-485 is part of the PCI Mezzanine Card [PMC] family of modular I/O components. The PMC-PARALLEL-485 provides 32 differential IO lines in one PMC slot. The IO lines are brought to a 68-pin SCSI 3 style connector and to the backplane connector. In addition, a bi-directional clock and clock enable differential pair are provided at the front panel.Each of the 32 differential pairs is programmable to be an input or an output. The lower 4 bits [0-3] are individually programmable. The remaining bits are programmed on a nibble basis. Input, Output, Termination active or disabled.The NRC1 version has three changes to the base design; A) The upper nibble is fixed to output B) The interrupts are supported with an added register programmable to create interrupts on both edges C) the upper nibble is supported with a mux to allow the bits [inputs] 24-27 to be mapped onto 28-31 or driven by the programmed output register.The IO are available as inputs in two forms. The data can be read directly without filtering or from a data latch which captures any detected 'hi' condition. The data can be selectively inverted and masked prior to the latch function. The data latches can be programmed to respond to a rising, falling or both edges, or simply to the voltage level of the signal. The direct read data is unaffected by the inversion, filtering, and masking. The output lines are driven, double clocked, from the output register.The 485 transceivers are selectively enabled for transmitting and always enabled for receiving. Separate input and output lines between the FPGA and the transceivers allow for local loop-back if the transceivers are enabled to transmit.Each differential pair has a 180Ω parallel termination resistor. Analog switches are programmed to activate the termination when the termination bit for an IO pair is set. The resistance stated includes the analog switch contribution. For cable terminated environments the analog switches and resistors can be programmed to be disabled.Eight “user bits” are supplied for user configuration control.A clock generator is provided which can be referenced to an external source, the local oscillator [optional] or the PCI clock. The generator has a programmable divider [12 bits].
SizeSingle wide PMC
Parallel Interface32 independent differential channels. Each channel can be an input or an output.
Clocks2 additional differential pairs for clock and clock enable.Software selectable direction control. Could be programmed for other purposes [FPGA].
State MachineAll bits are fed back through the FPGA to allow custom interfacing options.Contact the factory for implementation.
Counter TimersProgrammable
InterfaceRS-485, LVDS and mixed transceiver options. Also compatible with RS-422 requirements.
Termination ResistorSelectable switch plus resistor equivalent resistance.Selectable direction control.
Software Interface32 bit registers.Read-back of channel control registers and input registers. Read-write of control register for card configuration.
InterruptsAll IO Channels can be programmed to cause interrupts. Each channel is programmable to be masked, active hi, active low, edge triggered. Interrupts are mapped to INTA on PCI bus.
Power Requirement+5V, +3V
External ClockInput registers are programmable to capture data on the internal clock, user oscillator or external user supplied clock. Additionally an external clock enable input is provided to allow selective clocks to be gated at the register. SW can select internal or external source for clock and clock enable.
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Digital Parallel Interface PMC Modules
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