DYNAMIC ENGINEERING PMC-PARALLEL-485NG1 overview
Dynamic Engineering PMC-PARALLEL-485NG1 Digital Parallel Interface PMC Module with programmable counter timers, alternate interrupt implementation, clock generators and more. The PMC compatible PMC-Parallel-485-NG1 design adds 32 [RS-485 /RS-422] differential IO lines to one slot of your carrier boa...
Manufactured byDYNAMIC ENGINEERING
Part number or familyPMC-PARALLEL-485NG1
Product groupDigital Parallel Interface PMC Modules
What is DYNAMIC ENGINEERING PMC-PARALLEL-485NG1?
Dynamic Engineering PMC-PARALLEL-485NG1 Digital Pa.... Dynamic Engineering PMC-PARALLEL-485NG1 Digital Parallel Interface PMC Module with programmable counter timers, alternate interrupt implementation, clock generators and more. The PMC compatible PMC-Parallel-485-NG1 design adds 32 [RS-485 /RS-422] differential IO lines to one slot of your carrier boa...
Product details
Manufactured byDYNAMIC ENGINEERING
Product groupDigital Parallel Interface PMC Modules
DescriptionDynamic Engineering PMC-PARALLEL-485NG1 Digital Parallel Interface PMC Module with programmable counter timers, alternate interrupt implementation, clock generators and more.
OverviewThe PMC compatible PMC-Parallel-485-NG1 design adds 32 [RS-485 /RS-422] differential IO lines to one slot of your carrier board. 2 additional differential pairs are available for a clock & clock enable. The signals can be used to capture data with an external reference or programmed to be references for the rest of the system.Each channel is programmable to be an input or an output. The lower four bits are independent. The rest are programmed on a nibble basis. The IO remaining after special functions are available as inputs in two forms. The data can be read directly without filtering and from a data latch which captures any detected 'hi' condition. The data can be selectively inverted and masked prior to the latch function. The direct read data is unaffected by the inversion and masking. The output lines are directly driven from a register. The transceivers are selectively enabled for transmitting and always enabled for receiving. Separate input and output lines between the FPGA and the transceivers allow for local loop-back if the transceivers are enabled to transmit.Each channel is programmable to be terminated or not. The lower four bits are independent. The rest of the bits are programmed on a nibble [4 bit group] basis. Each differential pair has a parallel termination resistor. Analog switches are programmed to activate the termination when the termination bit for an IO pair is set. The resistance stated includes the analog switch contribution. For cable terminated environments the analog switches and resistors can be programmed to be disabled.Eight user bits are supplied for user configuration control. Two clock generators are provided. Each generator can be referenced to either the external source, the local oscillator [2 MHz] or the PCI clock/2. The generators are programmable [12 bits]. The generated frequencies are then used as the reference for two counters. One counter is 32 bits wide and the other is 14.The output of the counters is available via the PCI bus. The output of the 32 bit counter is captured based on the state of the 14 bit counter, and available from a second register. Interrupts can be generated when specific [programmed] counter bits roll over. The 32 bit counter can be used for Time of Day requirements with the 14 bit counter used to time events.An 8 bit user switch is provided to allow custom configurations to be easily and automatically configured with a common software driver. For example; the switch can be read through the status port and used to determine what the RX/TX configuration should be and any special characteristics for that implementation.All configuration registers support read and write operations for maximum software convenience. LW operations are supported.All of the data bits pass through the FPGA used to implement the PCI interface. Any or all bits can be used for custom state machine and IO functions. Custom termination options are also available. Please contact Dynamic Engineering with your requirements.A high density 68 pin SCSI III front panel connector provides system wiring.The PMC-PARALLEL-485 conforms to the PMC standard. This guarantees compatibility with multiple PMC Carrier boards. Because the PMC may be mounted on different form factors, while maintaining plug and software compatibility, system prototyping may be done on one PMC Carrier board, with final system implementation on a different one.
SizeSingle wide PMC
Parallel Interface32 independent differential channels. Each channel can be an input or an output.
Clocks2 additional differential pairs for clock and clock enable.Software selectable direction control. Could be programmed for other purposes [FPGA].
State MachineAll bits are fed back through the FPGA to allow custom interfacing options.Contact the factory for implementation.
Counter TimersProgrammable
InterfaceRS-485, LVDS and mixed transceiver options. Also compatible with RS-422 requirements.
Termination ResistorSelectable switch plus resistor equivalent resistance.Selectable direction control.
Software Interface32 bit registers.Read-back of channel control registers and input registers. Read-write of control register for card configuration.
InterruptsAll IO Channels can be programmed to cause interrupts. Each channel is programmable to be masked, active hi, active low, edge triggered. Interrupts are mapped to INTA on PCI bus.
Power Requirement+5V, +3V
External ClockInput registers are programmable to capture data on the internal clock, user oscillator or external user supplied clock. Additionally an external clock enable input is provided to allow selective clocks to be gated at the register. SW can select internal or external source for clock and clock enable.
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Digital Parallel Interface PMC Modules
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