DYNAMIC ENGINEERING cPCIBPMC overview
Dynamic Engineering cPCIBPMC Series cPCI-to-PMC Adapters / Carrier. cPCI 3U 4HP 1 Slot PMC Compatible Carriers.The cPCIBPMC3U64 is a 0 - 70C board design based ...
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Manufactured byDYNAMIC ENGINEERING
Product typecPCI-to-PMC Adapter
DescriptionDynamic Engineering cPCIBPMC Series cPCI-to-PMC Adapters / Carrier. cPCI 3U 4HP 1 Slot PMC Compatible Carriers.The cPCIBPMC3U64 is a 0 - 70C board design based on the 21154 bridge. The cPCIBPMC3U64ET is an extended temperature version carrier using a PLX 6466 bridge. The cPCIBpMC6UET is a 6U extended temperature carrier with two PMC slots. The PCI bus is interconnected to the PMC via 64 bit 66 MHz capable layout. The slower and more narrow device will determine the interface characteristics. The supplied dip-switch is used to control the bridge configuration. The user can select the clock rate, [33/66] on both buses and has access to the GPIO bits. PME and the Interrupt request lines are routed from the PMC to the cPCI connector.The PCI VIO is interconnected to the primary side of the bridge. The secondary side of the bridge has programmable VIO allowing 5V PMCs to be used in 3V systems and vice-versa. The voltage select pins are not installed on the cPCIBPMC. The bridge will automatically adapt to the PCI bus reference voltage. Many PMCs are "universal" and can work with 3.3 or 5V cPCI backplanes. The secondary side has a shunt for the user to select 5V or 3V operation.The cPCIBPMC follows the PMC specs for maximum power consumption and heat dissipation. The power is routed from the cPCI to PMC connectors with mini-planes each of which is rated for more than the maximum PMC draw. 3.3, 5, VIO, +12, -12The cPCIBPMC3U64ET has a low internal power dissipation. The dissipation is a function of the frequency and load from the installed PMC's. With cPCI J2 has two definitions - in a 64 bit PCI implementation J2 has the upper A/D and control signals and in a 32 bit PCI implemention J2 has the rear panel IO. The cPCIBPMC3U64 has the upper part of the PCI bus connected to J2. In addition the commonly used Etherenet and I2C pins from the Jn4 and Jn1 are connected to unused pins on J2 to allow rear panel IO for those signals. Please refer to the manual for the signal definitions.
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