CREDENCE KALOS 2 Series overview
Credence KALOS 2 Series Semiconductor Test Equipment The Kalos 2 test system is a general purpose test system with the additional features necessary to optimall...
Manufactured byCREDENCE
Part number or familyKALOS 2 Series
Product groupSemiconductor Test Equipment
Product details
Manufactured byCREDENCE
Product groupSemiconductor Test Equipment
DescriptionCredence KALOS 2 Series Semiconductor Test Equipment
OverviewThe Kalos 2 test system is a general purpose test system with the additional features necessary to optimally test non-volatile memories, embedded non-volatile memories, and high volume logic. As shown in Figure 1, its small size and highly integrated design optimizes test floor space and lowers the cost of testing. Use of common I/O pins and resources per pin allow testing and programming of logic pattern device tests and standard device under test (DUT) interfaces. Tester-per-DUT architecture allows each device test to proceed independently, maximizing throughput for nondeterministic parallel test flows. Handlers and probers are accommodated by design, with program loading and central control by way of a workstation computer.Performance features include a 100 MHz basic test rate, per-DUT redundancy analysis, per-DUT AC and DC test. Kalos 2 test systems have the capability to test all future sizes of memory, peripheral logic, and memory arrays of up to terabit data size andI/O pin counts in multiples of 96 to 768 I/O pins. The test head, with four modules, provides 36 independent test systems, each with 96 I/O pins, for a total of 3456 I/O pins. Each of the I/O pins has individually programmed tri-level voltages, current loads, and comparators.Each of the possible 36 Kalos 2 test systems in a test head has two dedicated central processing unit (CPU) Modules (ETX). As a result, Kalos 2 has none of the test overhead and restrictions of shared resource architecture test systems, where all devices must wait for the slowest device or when serial binning is mandated. With 36 x 96 pin (or 72 x 48 pin) DUTs simultaneously tested asynchronously in parallel—this sequence independence means each DUT is tested with maximum throughput.Each 48 I/O pin tester slice has its own CPU module, error capture RAM (ECR), and data buffer memory (DBM) for compatibility with existing Kalos 1 programs. It is possible for one tester controller to control up to four tester slices. In addition, when two 48 pin slices are controlled by one tester controller, any I/O pin can be assigned to any DUT physical pin or ECR pin. For parallel 96 pin tester configurations, the I/O’s are in blocks of 96 I/O pins. Complex sequential programming loops and redundancy analysis programs are executed independently, reducing the processor overhead of the test flow to an absolute minimum.Higher pin count test system configurations are accommodated by a unique controller design that provides software control from one controller to take synchronous master control of up to eight Kalos 2 systems. This allows each test head to be configured as: 72 sites of 48 I/O pins 36 sites of 96 I/O pins 16 sites of 192 pinsParallel operation of up to eight devices from one tester controller supports 576 DUTS with 6 I/O pins.
Manufacturer, product group, and supply
See who makes this product, where it belongs, and where available inventory may be listed.
Available from
Sourcing support available
Start a sourcing request