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MAX V Series

Altera · Low Power CPLDs

Altera MAX V Series

Altera MAX V Series overview

Altera MAX V Series Low Cost and Low Power CPLDs The MAX® V family of low cost and low power CPLDs offer more density and I/Os per footprint versus other CPLDs...

Manufactured byAltera
Part number or familyMAX V Series
Product groupLow Power CPLDs

Product details

Manufactured byAltera
Product groupLow Power CPLDs
DescriptionAltera MAX V Series Low Cost and Low Power CPLDs
OverviewThe MAX® V family of low cost and low power CPLDs offer more density and I/Os per footprint versus other CPLDs. Ranging in density from 40 to 2,210 logic elements (LEs) (32 to 1,700 equivalent macrocells) and up to 271 I/Os, MAX V devices provide programmable solutions for applications such as I/O expansion, bus and protocol bridging, power monitoring and control, FPGA configuration, and analog IC interface.MAX V devices feature on-chip flash storage, internal oscillator, and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX V CPLDs can help you meet your low power design requirement.
Key FeaturesLow-cost, low-power, and non-volatile CPLD architecture Instant-on (0.5 ms or less) configuration time Standby current as low as 25 µA and fast power-down/reset operation Fast propagation delay and clock-to-output times Internal oscillator Emulated RSDS output support with a data rate of up to 200 Mbps Emulated LVDS output support with a data rate of up to 304 Mbps Four global clocks with two clocks available per logic array block (LAB) User flash memory block up to 8 Kbits for non-volatile storage with up to 1000 read/write cycles Single 1.8-V external supply for device core MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors Schmitt triggers enabling noise tolerant inputs (programmable per pin) I/Os are fully compliant with the PCI-SIG® PCI Local Bus Specification, revision 2.2 for 3.3-V operation Hot-socket compliant Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990

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Manufactured by Altera View Altera profile
Product group Low Power CPLDs Explore Low Power CPLDs
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