Alliance Semiconductor AS7C256 overview
Alliance Semiconductor AS7C256 High Performance 32Kx8 CMOS SRAM Organization: 32,768 words × 8 bits High speed– 10/12/15/20/25/35 ns address access time– 3/3/4/5/6/8 ns output enable access time Low power consumption– Active: 660 mW max (10 ns cycle)– Standby: 11 mW max, CMOS I/O 2.75 mW ma...
What is Alliance Semiconductor AS7C256?
Alliance Semiconductor AS7C256 High Performance 32Kx8 CMOS SRAM Organization: 32,768 words × 8 bits High speed– 10/12/15/20/25/35 ns address access time– 3/3/4/5/6/8 ns output enable access time Low power consumption– Active: 660 mW max (10 ns cycle)– Standby: 11 mW max, CMOS I/O 2.75 mW ma...
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Manufactured byAlliance Semiconductor
Product groupModules
DescriptionAlliance Semiconductor AS7C256 High Performance 32Kx8 CMOS SRAM
Key FeaturesOrganization: 32,768 words × 8 bits High speed– 10/12/15/20/25/35 ns address access time– 3/3/4/5/6/8 ns output enable access time Low power consumption– Active: 660 mW max (10 ns cycle)– Standby: 11 mW max, CMOS I/O 2.75 mW max, CMOS I/O, L version– Very low DC component in active power 2.0V data retention (L version Equal access and cycle times Easy memory expansion with CE and OE inputs TTL-compatible, three-state I/O 28-pin JEDEC standard packages– 300 mil PDIP and SOJ Socket compatible with 7C512 and 7C1024– 330 mil SOIC– 8×13.4 TSOP ESD protection > 2000 volts Latch-up current > 200 mA
OverviewThe AS7C256 is a high-performance CMOS 262,144-bit Static Random Access Memory (SRAM) organized as 32,768 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20/25/35 ns with output enable access times (tOE) of 3/3/4/5/6/8 ns are ideal for high-performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.When CE is HIGH the device enters standby mode. The standard AS7C256 is guaranteed not to exceed 11 mW power consumption in standby mode; the L version is guaranteed not to exceed 2.75 mW, and typically requires only 500 µW. The L version also offers 2.0V data retention, with maximum power consumption in this mode of 300 µW. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output-enable (OE) or write enable (WE).A read cycle is accomplished by asserting chip enable (CE) and output-enable (OE) LOW, with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When the chip enable or output enable is HIGH, or write enable is LOW, output drivers stay in high-impedance mode.All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C256 is packaged in all high-volume industry-standard packages.
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